(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for creating an Electrostatic Discharge (ESD) protection circuit for well-triggered PMOS devices.
(2) Description of the Prior Art
In deep submicron CMOS technology, ESD damage has become one of the main reliability concerns. Processing techniques that are applied in advanced CMOS technology procedures can lead to degradation of the performance of ESD circuits that are part of Integrated Circuits (IC's). Examples of these advanced processing techniques are the formation of Lightly Doped Drain (LDD) regions in the MOSFET devices, the formation of salicided drain/source surface regions for MOSFET devices and the formation of extremely thin gate oxide layers underneath the gate electrodes of MOSFET devices. To improve the performance of ESD circuitry of deep submicron CMOS IC's, a number of design methods and approaches have been proposed and applied to I/O cells and Power/Ground cells of semiconductor devices. These methods include ESD protection devices, ESD protection circuits, ESD layout technique and process modifications.
For general industrial applications, the input/output pins of the Integrated Circuits must be able to sustain extreme voltage levels when in contact with an ESD source in excess of 2000 volts. In order to achieve this objective, ESD protection circuits are placed around the I/O pads of the IC's such that these ESD protection circuits protect the IC's against potential ESD damage. The ESD protection circuits shunt the electrostatic charges that originate in the ESD source away from the IC thereby preventing damage to the IC.
It had been shown that ESD clamp circuits that are implemented between power (VDD) and ground lines (VSS) can improve the ESD performance of the whole chip. For ESD clamp circuits of the VDD-to-VSS type, several patents have been filed during recent years [1-5]. Among these patents, some provide for the application of gate-driven techniques [6-7] while others apply substrate-driven techniques [8-9]. In some patents, for instance [1-2] and [4-5], NMOS has been used as an ESD clamp circuit while PMOS has been used as an ESD clamp circuit in other patents [3].
FIG. 1 shows the VDD-to-VSS ESD clamp circuit that is implemented using a resistor 10, a capacitor 12, an inverter 14 and an NMOS device 16 having a load resistance 18. This example is further detailed and is representative of the U.S. patents under References [1-2]. This circuit can help to efficiently turn on the NMOS device by making use of the delay of the RC time constant. For general cases, the value of the RC time constant is designed in the order of micro-seconds.
The VDD-to-VSS ESD clamp circuit implemented using a resistor 10, a capacitor 12 and a PMOS device 20 is shown in FIG. 2. This example is further detailed and is representative of the U.S. patents under Reference [3]. The delay caused by the RC time constant of the circuit, which is determined by the values of the resistor 10 and the capacitor 12, can help to turn on the PMOS device 20 if the ESD overstress occurs between the VDD and VSS power rails.
In other patents [4-5], the VDD-to-VSS ESD clamp circuit has been implemented using the gate-coupled effect, the schematic diagram for this application is shown in FIG. 3. When the ESD overstress voltage is between the VDD and VSS power rails, the voltage of the node N (Vg) is coupled to a high voltage VDD and causes the NMOS device 22 to turn on. After the NMOS device 22, having a load resistance of 24, is turned on, thereby passing the ESD current from VDD to VSS. Therefore, the ESD level of this ESD clamp circuit is improved [6-7]. However, the gate-driven effect has been confirmed to cause a sudden degradation on the ESD level of ESD-protection devices when the voltage of the gate is too high [8-9]. On the other hand, the substrate-triggered effect can continue to increase the ESD level of ESD-protection devices [9]. Therefore, the substrate-triggering technique is used to design the efficient ESD clamp circuit in this invention. It must further be realized that while using the p-substrate CMOS process, it is easier to control the voltage of the N-well than it is to control the voltage of the p-substrate. This is because the p-substrate must be connected to ground voltage in the integrated circuits, while the N-well can be isolated from other voltage sources.
The following U.S. patents and other publications relate to ESD circuits.    1) K. Lee, “Power rail ESD protection circuit,” U.S. Pat. No. 5,237,395, 1993.    2) W. Miller, “Electrostatic discharge detection and clamp control circuit,” U.S. Pat. No. 5,255,146, 1993.    3) D. Puar, “Shunt circuit for electrostatic discharge protection,” U.S. Pat. No. 5,287,241, 1994.    4) C. Duvvury and R. N. Rountree, “Output buffer with improved ESD protection,” U.S. Pat. No. 4,855,620, 1989.    5) M. D. Ker, C. Y. Wu, T. Cheng, C. N. Wu, and T. L. Yu, “Capacitor-couple electrostatic discharge protection circuit,” U.S. Pat. No. 5,631,793, 1997.    6) C. Duvvury, D. Briggs, J. Rodrigues, F. Carvajal, A. Young, D. Redwine, and M. Smayling, “Efficient npn operation in high voltage NMOSFET for ESD robustness,” Tech. Dig. of IEDM, pp. 345-348, 1995.    7) J. Chen, A. Amerasekera, and C. Duvvury, “Design methodology for optimized gate driven ESD protection circuits in submicron CMOS processes,” Proc. of EOS/ESD Symp., pp. 230-239, 1997.    8) A. Amerasekera, C. Duvvury, V. Reddy, and M. Rodder, “Substrate triggering and salicide effects on ESD performance and protection circuit design in deep submicron CMOS processes”, Tech. Dig. of IEDM, pp. 547-550, 1995.    9) T. Y. Chen, M. D. Ker, and C. Y. Wu, “Experimental investigation on the HBM ESD characteristics of CMOS devices in a 0.35-um silicided process,” International Symposium on VLSI Technology, Systems, and Applications, p. 35-38, 1999.